Cold cathode fluorescent lighting is widely used for solid-state computer display backlighting. High voltage power supplies designed to drive modern cold cathode fluorescent lamps (CCFLs) typically employ application-specific integrated circuits (ICs) to control the CCFL brightness. This is usually accomplished by controlling the current in the primary winding circuit of a Royer-class converter using a first level of high-frequency pulse width modulation (PWN) (e.g., at a frequency of approximately 350 kHz), and a second, additional level of low-frequency (e.g., 200 Hz) on-off modulation of the PWM current control signal. An example of an IC commonly used in this application is the Linear Technology LT1768, a high-power CCFL controller. Details of the LT1768 circuitry can be obtained by referring to publicly available documentation, such as the data sheet information published at http://www.linear-tech.com/go/dnLT1768, as well as the article “High Power Desktop LCD Backlight Controller Supports Wide Dimming Ratios While Maximizing Lamp Lifetime” by Richard Philpott of Linear Technology, Design Note 264, August 2001, published at http://www.linear-tech.com/pub/documnent.html?pub_type=desn&document=292, both references being incorporated herein by reference in their entirety.
FIG. 1 is a representative schematic diagram of a prior art power supply which makes use of an LT1768 to operate one or more CCFLs. In this case, the circuitry includes a dual-grounded lamp backlight inverter that operates from an input voltage VIN of about 9-24 VDC. The Royer converter 100 delivers current ranging from about 0-9 mA to each CCFL 102. Using the circuit values shown, the LT1768 IC 104 operates as a 350 kHz fixed frequency, current mode, pulse width modulator to control the Royer converter 100. As is typical of controller ICs of this type, the second level of low-frequency PWM on-off modulation frequency is usually set by selecting the value of an external timing capacitor, CT, for example, connected to a specific pin (e.g., the PWM modulation on-off frequency timing input 108) on the controller IC 104. Considering the circuit values shown in FIG. 1, the low-frequency oscillation frequency occurs at about 220 Hz.
A representation of the low-frequency oscillation voltage present at the timing input 108 of the prior art LT1768 IC 104 of FIG. 1 can be seen in FIG. 2. During operation of the PWM controller IC, an internal current source is first applied to the timing input at time t=t0 so as to produce a positive-going voltage ramp 216 at the timing input, due to the charging action of the capacitor CT. When the voltage at the CT pin 108 reaches a first specified value (e.g., an upper threshold voltage 218), the internal current source is removed from the timing input, and an internal current sink (usually sinking a larger current value than the internal current source supplies) is applied. The result is a rapidly falling voltage ramp 220 (relative to the slope of the current-source, positive-going ramp 216) due to the discharging action of the capacitor CT at the timing input. When the voltage at the CT pin reaches a second specified value (e.g., a lower threshold voltage 222 which is less than the upper threshold voltage 218), the internal current sink is removed from the timing input. The internal current source is then re-applied to the timing input, initiating another charge/discharge cycle of the capacitor CT. This occurs at t=tp, which is the natural period of the PWM low-frequency modulation for the IC (e.g., about 5 milliseconds at 220 Hz).
Some controller ICs use resistive networks instead of current sources/sinks to charge/discharge the capacitor CT. In this case, the low-frequency modulation voltage waveform at the timing input will possess a ramp with an exponential slope, rather than a linear slope. Otherwise, the operation is essentially the same as described previously.
In the case of low-frequency, on-off duty cycle modulation of the PWM waveform in CCFL converters, it is usually desirable to be able to lock the modulation frequency to some multiple of the display refresh rate (or some other critical parameter) to avoid visual interference effects on the display. In other types of switching power supplies it is also be desirable to lock the PWM oscillation frequency to a known time base in order to avoid radio interference and other undesirable effects.
A typical method of synchronizing the low-frequency operation of controllers for CCFL inverters and other PWM power supply circuits involves injection-locking the PWM timing oscillator to a desired frequency. For example, short duration pulses 224 can be injected into a junction formed between the low side of the capacitor CT and a resistor (e.g., resistor 109 in FIG. 1) connected to ground. This causes the upper threshold voltage of the ramped modulation waveform to be reached at a point in time t=tS just after the injection takes place, and the discharge portion of the oscillator cycle begins immediately after the pulse is removed. While this has the effect of ending the charging portion of the cycle sooner than would otherwise occur (e.g., at I=tE), the pulse width t, of the injection signal must be kept very short or else the discharge portion of the modulation oscillator cycle will be delayed and “held high” by the synchronization pulse 224.
To complicate matters, some controllers cannot tolerate voltages at the timing input which exceed the upper threshold voltage 218 value by more than a nominal amount. This means that the injection pulse amplitude V, must also be carefully controlled to avoid exceeding the specified value required by the controller IC, since it adds to the upper threshold voltage 218 to form a maximum CT voltage 225 prior to discharge, at least to some degree. For example, in the case of the LTI 768, the upper threshold voltage value should be limited to the same voltage that is applied to a programming pin (i.e., the “PWM” pin in FIG. 1).
To deal with these concerns, the manufacturer suggests taking the approach shown in FIG. 3, which is a representative schematic diagram of a prior art synchronization circuit having a controlled injection pulse. This circuit 326 can be used as a synchronizing mechanism for the prior art power supply of FIG. 1. The common trait shared by standard injection locking techniques, previously described, as well as the more complex example shown in FIG. 3, is that several parts must be used, which increases overall circuit cost. Standard synchronizing techniques also waste power because they inject a current pulse directly into the timing circuitry, including CT and/or other elements connected to it, such as a resistor (e.g.; resistor 109 in FIG. 1). The injection point is also typically a low impedance point, resulting in pulse currents of an amplitude sufficient to produce conducted and/or radiated electromagnetic interference. Finally, standard injection locking techniques tend to hall or “freeze” the operation of internal PWM oscillator circuitry 328 until the synchronizing pulse is removed when approaches less sophisticated than that shown in FIG. 3 are used.
Thus, there is a need in the art to provide an improved mechanism for synchronizing circuitry, such as PWM controller circuitry, to a selected frequency. Such an approach should use a minimal number of external parts. An apparatus and method should therefore be developed which act to synchronize the operation of selected circuitry, in conjunction with internal current sources/sinks, so that the affect on the oscillation waveform, other than regulating its period, is minimal. Such an apparatus and method should act to safely control the amplitude of the timing voltage waveform, such that maximum values are not exceeded, while not unduly restricting the length of the synchronizing pulse.